HP DV2000 (965GM) - WISTRON PAMIRS UMA - REV -3, HP COMPAQ
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5
4
3
2
1
Pamirs UMA Block Diagram
SYSTEM DC/DC
TPS51120
INPUTS
OUTPUTS
5V_S3
Project code : 91.4S401.001
PCB P/N :06228
Revision : SB
Intel CPU
DCBATOUT
3V_AUX_S5
CLK GEN
Meron 2M/4M SV
FSB:667 or 800 MHz
SYSTEM DC/DC
D
D
MAX8743
ICS9LPRS355AKLFT-GP
4,5,6
INPUTS
OUTPUTS
3
CRT
RGB CRT
15
1D5V_S0
Host BUS
533/667MHz
DCBATOUT
1D8V_S3
LVDS
LCD
SYSTEM DC/DC
16
DDRII
533/667
ISL6269CRZ
Slot 0
Crestline-GM/GML
AGTL+ CPU I/F
INTEGRATED GRAHPICS
DDRII 667 Channel A
13
INPUTS
DCBATOUT
OUTPUTS
1D05V_S0
TVOUT
DDR I/F
SVIDEO
15
DDRII
533/667
Slot 1
DDR II 667 Channel B
PCIE x 16
LVDS, CRT I/F
MAXIM CHARGER
14
7,8,9,10,11,12
MAX8725
INPUTS
OUTPUTS
C
1394
1394
DMI I/F
100MHz
C
BT+
Ricoh
R5C832
25
CAMERA
DCBATOUT
18V 3.0A
32
5V 100mA
SD/SDIO/MMC
MS/MS Pro/xD
PCI
CardReader
INTEL
BLUE
TOOTH
25
24,25
CPU DC/DC
32
MAX8736ETL
ICH8-M
USB x 3
USB 2.0
INPUTS
OUTPUTS
23
10/100 NIC
LCI
10 USB 2.0/1.1 ports
(10/100/1000Mb)
RJ45
CONN
Marvell 88E8039
VCC_CORE
27
ETHERNET
SATA
HDD
DCBATOUT
28
High Definition Audio
23
0.844~1.3V
44A
ATA 66/100
PATA
ODD
AMOM
MODEM
ACPI 1.1
LPC I/F
23
PCB LAYER
B
RJ11
CONN
B
HD Audio
TPM
SLB9635T
34
29
CX20548
PCI/PCI BRIDGE
LPC Bus
L1:
Signal 1
18,19,20,21
INTERNAL
ARRAY MIC
L2:
GND
HD AUDIO
CODEC
CX20549-12Z
L3:
Signal 2
MIC IN
L4:
Signal 3
KBC
PCIE+USB 2.0
LINE OUT
29
ENE KB3910SF
L5:
VCC
Signal 4
Ricoh
R5538
31
L6:
SPDIF
28
Flash ROM
1MB
OP AMP
Thermal
& Fan
33
Mini-Card
Mini-Card
Capacity
Button
Touch
Pad
Int.
KB
APA2031
New Card
CIR
802.11a/b/g
WWAN
30
A
<Core Design>
<Core Design>
<Core Design>
A
G792
28
26
26
32
32
32
22
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH
SPEAKER
DOCK
10/100
Ethernet
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
CRT
MIC IN
LINE OUT
S/PDIF
TVOUT
CIR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Friday, May 18, 2007
Friday, May 18, 2007
Friday, May 18, 2007
Sheet
Sheet
Sheet
1
1
1
of
of
of
41
41
41
5
4
3
2
1
A
B
C
D
E
INTEL ICH8-M STRAP PIN
19,21
+RTCVCC
+RTCVCC
1D05V_S0
1D25V_S0
1D2V_LAN_S5
4,5,6,7,9,10,11,19,21,38,41
1D05V_S0
3,7,10,21,38
1D25V_S0
Signal
Usage/When Sampled
Comment
XOR Chain Entrance Strap
27
1D2V_LAN_S5
HDA_SDOUT
XOR Chain Entrance/
PCIE Port Config 1 bit1,
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
ICH_RSVD
tp3
AZ_DOUT_ICH
Description
28
1D5V_NEW_S0
1D5V_NEW_S0
0
0
RSVD
4
4
0
1
Enter XOR Chain
5,10,17,19,20,21,26,28,37,38,41
1D5V_S0
1D5V_S0
1
0
Normal Operation(default)
1
1
Set PCIE port cofig bit1
7,10,11,13,14,37,38,41
1D8V_S3
1D8V_S3
HDA_SYNC
PCIE Port Config 1 bit0,
Rising Edge of PWROK.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
27,28
2D5V_LAN_S5
2D5V_LAN_S5
GNT2#
PCIE Port Config 2 bit0,
Rising Edge of PWROK.
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
29,30
3D3V_AUD_S0
3D3V_AUD_S0
19,31,32,33,36,39,40
3D3V_AUX_S5
3D3V_AUX_S5
3D3V_LAN_S5
GPIO20
Reserved
Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
27,28
3D3V_LAN_S5
3,4,7,9,10,11,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36,41
3D3V_S0
3D3V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all
cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
A16 swap override strap
low = A16 swap override enable
high = default
GNT3#
Top-Block Swap Override.
Rising Edge of PWROK.
17,18,20,21,22,26,27,28,29,31,34,36,39,41
3D3V_S5
3D3V_S5
PCI_GNT#3
22,29,31,34,36
5V_AUX_S5
5V_AUX_S5
BOOT BIOS Strap
16,23,32,33,34,36,37,38
5V_S3
5V_S3
PCI_GNT#0
SPI_CS#1
BOOT BIOS Location
SPI
GNT0#
SPI_CS1#
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
15,16,17,20,21,22,23,26,29,30,31,32,33,34,35,41
5V_S0
5V_S0
0
1
1
0
PCI
LPC(Default)
16,21,34,37,38
5V_S5
5V_S5
AD+
1
1
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
sampled.
17,39,40,41
AD+
Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
16,17,34,35,36,37,38,39,41
DCBATOUT
DCBATOUT
SM_INTVRMEN
integrated VccLan1_05VccCL1_05
High=Enable Low=Disable
13,14,38,41
DDR_VREF_S0
DDR_VREF_S0
3
3
Integrated VccLAN1_05
VccCL1_05 VRM enable
/Disable. Always sampled.
Enables integrated VccLAN1_05,VccCL1_05 VRM
when sampled high
7,13,14,38
DDR_VREF_S3
DDR_VREF_S3
LAN100_SLP
LAN100_SLP
High=Enable Low=Disable
22,31,33,39
KBC_3D3V_AUX
KBC_3D3V_AUX
16
VCC_CORE_S0
LCDVDD_S0
LCDVDD_S0
VCC_CORE_S0
SATALED#
PCIE LAN REVERSAL.Rising
Edge of PWROK.
This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)
DEFAULE HIGH
5,6,35
No Reboot Strap
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
SPKR
No Reboot.
Rising Edge of PWROK.
SPKR
LOW = Defaule
High=No Reboot
TP3
XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing.
INTEL ICH8-M INTEGRATED
PULL-UPS and PULL-DOWNS
SIGNAL
Internal Pull-Up.If sampled low,the Flash Descriptor
Security will be overidden.if high,the Security
measures defined in the Flash Descriptor will be in
effect.
GPIO33/
HDA_DOCK_EN#
Flash Descriptor Security
Override Strap
Rising Edge of PWROK.
8.2K PULL HIGH
This should only be used in manufacturing
environments
Resistor Type/Value
HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
PULL-DOWN 20K
NONE
2
2
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN
PULL-UP 20K
CFG Strap
LOW 0
HIGH 1
PULL-DOWN 20K
CFG 5
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
º
DMI X 2
DMI X 4
CFG 8
LAN_RXD[2:0]
º
Low Power PCI Express
Normal
Low Power mode
CFG 9
LDRQ[0]
º
PCI Express Graphics
Lane Reversal
Lane Reversal
Normal Mode(Lanes
number in order)
LDRQ[1]/GPIO23
CFG 16
º
FSB Dynamic ODT
Disabled
Enabled
PME#
PWRBTN#
SATALED#
CFG 19
º
DMI Lane Reserved
Normal Operation
Reserved Lane
CFG 20
Only PCIE or SDVO
is operation
PCIE and SDVO are
operation simultaneous
º
Concurrent SDVO/PCIE
SDVO_CTRL_DATA
SDVO Present
NO SDVO Card
Present
SDVO Card Present
SPI_CS1#
º
SPI_CLK
<Core Design>
<Core Design>
<Core Design>
CFG 12
XOR/ALL-Z
SPI_MOSI
SPI_MISO
TACH_[3:0]
1
1
CFG 13
LL(00)
LH(01)
HL(10)
HH(11)
Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SPKR
PULL-DOWN 20K
Title
Title
Title
TP[3]
PULL-UP 20K
Table of Content
Table of Content
Table of Content
USB[9:0][P,N]
CL_RST#
PULL-DOWN 15K
TBD
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Tuesday, May 22, 2007
Tuesday, May 22, 2007
Tuesday, May 22, 2007
Sheet
Sheet
Sheet
2
2
2
of
of
of
41
41
41
A
B
C
D
E
5
4
3
2
1
3D3V_S0
3D3V_S0_CK505
L11
L11
2/12
3D3V_S0_CK505
3D3V_S0_CK505_IO
2/12
1
2
0R0603-PAD
0R0603-PAD
C484
C195
C448
C448
C439
C442
C442
C475
C440
C445
DY
DY
DY
DY
X1
X1
CLK_XTAL_IN
CLK_XTAL_OUT
1
2
X-14D31818M-40GP
X-14D31818M-40GP
D
D
C186
SC27P50V2JN-2-GP
C185
SC27P50V2JN-2-GP
U21
U21
2/12
1D25V_S0
R650
R650
3D3V_S0
CLK_CPU_BCLK1
RN29
RN29
SRN0J-6-GP
SRN0J-6-GP
1
2
61
1
2
4
CLK_CPU_BCLK
4
CPUT0
3D3V_S0_CK505_IO
CLK_CPU_BCLK1#
CLK_MCH_BCLK1
60
3
CLK_CPU_BCLK#
4
CPUC0
DUMMY-R3
DUMMY-R3
CLK_XTAL_IN
L36
L36
3
58
RN32
RN32
1
2
4
SRN0J-6-GP
SRN0J-6-GP
CLK_MCH_BCLK
7
X1
CPUT1_F
C190
C190
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
CLK_XTAL_OUT
CLK_MCH_BCLK1#
1
2
2
57
3
CLK_MCH_BCLK#
7
X2
CPUC1_F
0R0603-PAD
0R0603-PAD
1
2
54
CLK_CPU_XDP1
CLK_CPU_XDP1#
TP103
TP103
CPUT2_ITP/SRCT8
C212
C441
C466
C459
C459
C465
C200
C206
53
TP104
TP104
2/12
CPUC2_ITP/SRCC8
C446
FSA
1
2
17
20
CLK_48M_ICH
USB_48MHZ/FSLA
12/12
DY
DY
R159
R159
33R2J-2-GP
33R2J-2-GP
CLK_PCIE_LAN1
CLK_PCIE_LAN1#
RN36
RN36
SRN0J-6-GP
SRN0J-6-GP
51
1
2
4
SRCT7/CR#_F
CLK_PCIE_LAN
27
50
3
CLK_PCIE_LAN#
27
SRCC7/CR#_E
45
20
H_STP_PCI#
PCI_STOP#
CLK_PCIE_MINI1_1
RN44
RN44
SRN0J-6-GP
SRN0J-6-GP
44
48
1
2
4
CLK_PCIE_MINI1
26
20
H_STP_CPU#
CPU_STOP#
SRCT6
CLK_PCIE_MINI1_1#
47
3
CLK_PCIE_MINI1#
26
SRCC6
CLK_PCIE_NEW1
41
2
3
4
CLK_PCIE_NEW
28
SRCT10
CLK_PCIE_NEW1#
7
42
1
CLK_PCIE_NEW#
28
13,14,20
ICH_SMBDATA
ICH_SMBCLK
SCLK
SRCC10
RN42
RN42
SRN0J-6-
G
P
SRN0J-6-GP
6
1
2
13,14,20
SDATA
3D3V_S0
40
R184
R184
10KR2J-3-GP
10KR2J-3-GP
SRCT11/CR#_H
NEWCARD_CLKREQ#
28
R183
R183
63
39
1
2
20
CK_PWRGD
CK_PWRGD/PD#
SRCC11/CR#_G
C
C
12/18
DY
DY
10KR2J-3-GP
10KR2J-3-GP
CLK_PCIE_MINI2_1
37
2
3
4
SRCT9
CLK_PCIE_MINI2
26
12/18
38
CLK_PCIE_MINI2_1#
1
CLK_PCIE_MINI2#
26
SRCC9
RN41
RN41
SRN0J-6-GP
SRN0J-6-GP
8
20
CLKSATAREQ#
PCI0/CR#_A
CLK_MCH_3GPLL1
10
34
2
3
4
CLK_MCH_3GPLL
7
7
CLKREQ#_B
PCI1/CR#_B
SRCT4
R143
R143
33R2J-2-GP
33R2J-2-GP
PCI2_TME
CLK_MCH_3GPLL1#
1
2
11
35
1
CLK_MCH_3GPLL#
7
33
PCLK_FWH
PCI2/TME
SRCC4
RN40
RN40
SRN0J-6-GP
SRN0J-6-GP
R150
R150
1
DY
DY
2
33R2J-2-GP
33R2J-2-GP
12
34
CLK_PCI_TCG
PCI3
R151
R151
33R2J-2-GP
33R2J-2-GP
27_SEL
CLK_PCIE_ICH1
1
2
13
31
2
3
4
31
PCLK_KBC
CLK_PCIE_ICH
20
PCI4/27_SELECT
SRCT3/CR#_C
R153
R153
33R2J-2-GP
33R2J-2-GP
ITP_EN
CLK_PCIE_ICH1#
1
2
14
32
1
18
CLK_PCI_ICH
CLK_PCIE_ICH#
20
PCI_F5/ITP_EN
SRCC3/CR#_D
RN39
RN39
SRN0J-6-GP
SRN0J-6-GP
R152
R152
33R2J-2-GP
33R2J-2-GP
1
2
24
PCLK_PCM
CLK_PCIE_SATA1
CLK_PCIE_SATA1
28
2
3
4
CLK_PCIE_SATA
19
SRCT2/SATAT
CLK_PCIE_SATA1#
CLK_PCIE_SATA1#
29
1
R382
R382
CLK_PCIE_SATA#
19
SRCC2/SATAC
RN38
RN38
SRN0J-6-GP
SRN0J-6-GP
FSB
64
FSLB/TEST_MODE
1
2
FSC
5
01/31
10/24
20
CLK_14M_ICH
REF0/FSLC/TEST_SEL
MCH_SSCDREFCLK1
24
2
3
4
MCH_SSCDREFCLK
7
27MHZ_NONSS/SRCT1/SE1
MCH_SSCDREFCLK1#
55
25
1
MCH_SSCDREFCLK#
7
33R2J-2-GP
33R2J-2-GP
NC#55
27MHZ_SS/SRCC1/SE2
RN33
RN33
SRN0J-6-GP
SRN0J-6-GP
20
CLK_MCH_DREFCLK1
2
3
4
SRCT0/DOTT_96
CLK_MCH_DREFCLK
7
3D3V_S0_CK505
01/31
CLK_MCH_DREFCLK1#
21
1
CLK_MCH_DREFCLK#
7
SRCC0/DOTC_96
RN31
RN31
SRN0J-6-GP
SRN0J-6-GP
DY
R385
10KR2J-3-GP
ICS9LPRS355AKLFT-GP
ICS9LPRS355AKLFT-GP
12/20
PCI2_TME
B
B
3D3V_S0_CK505
R386
10KR2J-3-GP
R386
10KR2J-3-GP
DY
DY
R141
10KR2J-3-GP
R141
10KR2J-3-GP
FS_C FS_B FS_A CPU
1 0 1 100M
0 0 1 133M
0 1 0 200M
0 1 1 166M
DY
DY
3D3V_S0_CK505
27_SEL
R142
10KR2J-3-GP
R379
10KR2J-3-GP
27_SEL PIN 20 PIN 21 PIN 24 PIN 25
0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100
1 SRCT0 SRCC0 27M_NSS 27M_SS
ITP_EN Output
0 SRC8
1 CPU_ITP
FSC
1
2
5
CPU_BSEL2
ITP_EN
R381
R381
10KR2J-3-GP
10KR2J-3-GP
1
2
FSB
FSA
5
CPU_BSEL1
R163
R163
0R0402-PAD
0R0402-PAD
R378
10KR2J-3-GP
R378
10KR2J-3-GP
1
2
5
CPU_BSEL0
DY
DY
R160
R160
2K2R2J-2-GP
2K2R2J-2-GP
R149
R149
1KR2J-1-GP
1KR2J-1-GP
1
2
MCH_CLKSEL0
7
R134
R134
1KR2J-1-GP
1KR2J-1-GP
1
2
MCH_CLKSEL1
7
<Variant Name>
<Variant Name>
<Variant Name>
A
A
R377
R377
1KR2J-1-GP
1KR2J-1-GP
1
2
MCH_CLKSEL2
7
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Design Note:
1. All of Input pin didn't have internal pull up resistor.
2. Clock Request (CR) function are enable by registers.
3. CY28548 integrated serial resistor of differential clock,
so put 0 ohm serial resistor in the schematic.
Title
Title
Title
Clock generator CY28548
Clock generator CY28548
Clock generator CY28548
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Monday, May 21, 2007
Monday, May 21, 2007
Monday, May 21, 2007
Sheet
Sheet
Sheet
3
3
3
of
of
of
41
41
41
5
4
3
2
1
5
4
3
2
1
7
H_A#[3..35]
U53A
U53A
1 OF 4
1 OF 4
1D05V_S0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_ADS#
H_BNR#
H_BPRI#
J4
H1
H_ADS#
7
A3#
ADS#
L5
E2
A4#
BNR#
H_BNR#
7
L4
G5
A5#
BPRI#
H_BPRI#
7
K5
A6#
H_DEFER#
D
M3
H5
D
H_DEFER#
7
A7#
DEFER#
H_DRDY#
R114
56R2J-4-GP
N2
F21
A8#
DRDY#
H_DRDY#
7
J1
E1
H_DBSY#
A9#
DBSY#
H_DBSY#
7
N3
A10#
H_BR0#
P5
F1
H_BR0#
7
A11#
BR0#
P2
A12#
L2
D20
H_IERR#
A13#
IERR#
H_INIT#
P4
B3
A14#
INIT#
H_INIT#
19
P1
A15#
H_LOCK#
R1
H4
H_LOCK#
7
A16#
LOCK#
M1
7
H_ADSTB#0
ADSTB0#
H_RESET#
C1
RESET#
H_RESET#
7
H_REQ#0
H_REQ#2
H_REQ#3
H_RS#0
K3
F3
7
H_REQ#0
REQ0#
RS0#
H_RS#0
7
H_REQ#1
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
H2
F4
7
H_REQ#1
REQ1#
RS1#
H_RS#1
7
K2
G3
7
H_REQ#2
REQ2#
RS2#
H_RS#2
7
J3
G2
7
H_REQ#3
REQ3#
TRDY#
H_TRDY#
7
H_REQ#4
L1
7
H_REQ#4
REQ4#
G6
HIT#
H_HIT#
7
H_A#17
Y2
E4
A17#
HITM#
H_HITM#
7
H_A#18
H_A#19
U5
A18#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
TP68
TP68
R3
AD4
A19#
BPM0#
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
TP91
TP91
2/12
W6
AD3
A20#
BPM1#
U4
AD1
TP93
TP93
A21#
BPM2#
TP101
TP101
Y5
AC4
A22#
BPM3#
TP102
TP102
U1
AC2
A23#
PRDY#
R4
AC1
A24#
PREQ#
T5
AC5
A25#
TCK
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
T3
AA6
A26#
TDI
W2
AB3
A27#
TDO
W5
AB5
A28#
TMS
Y4
AB6
A29#
TRST#
U2
C20
A30#
DBR#
XDP_DBRESET#
20
V4
A31#
H_A#32
W3
A32#
CPU_PROCHOT#
35
THERMAL
THERMAL
H_A#33
AA4
C
A33#
C
H_A#34
H_A#35
AB2
1
2
A34#
1D05V_S0
R122
R122
68R3J-GP
68R3J-GP
AA3
D21
A35#
PROCHOT#
H_ADSTB#1
H_THERMDA
H_THERMDC
V1
A24
7
H_ADSTB#1
ADSTB1#
THRMDA
H_THERMDA
22
B25
THRMDC
H_THERMDC
22
H_A20M#
H_IGNNE#
A6
19
H_A20M#
A20M#
H_FERR#
H_THERMTRIP#
A5
C7
19
H_FERR#
FERR#
THERMTRIP#
H_THERMTRIP#
7,19
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
C4
19
H_IGNNE#
IGNNE#
D5
19
H_STPCLK#
STPCLK#
HCLK
HCLK
CLK_CPU_BCLK
CLK_CPU_BCLK#
C6
A22
19
H_INTR
CLK_CPU_BCLK
3
LINT0
BCLK0
B4
A21
19
H_NMI
CLK_CPU_BCLK#
3
LINT1
BCLK1
A3
19
H_SMI#
SMI#
TPAD28
TPAD28
TP9
TP9
CPU_RSVD01
CPU_RSVD03
M4
RSVD#M4
TPAD28
TPAD28
TP10
TP10
CPU_RSVD02
CPU_RSVD04
CPU_RSVD06
CPU_RSVD07
CPU_RSVD08
CPU_RSVD09
CPU_RSVD10
CPU_RSVD11
N5
RSVD#N5
TPAD28
TPAD28
TP5
TP5
T2
RSVD#T2
TPAD28
TPAD28
TP7
TP7
V3
RSVD#V3
TPAD28
TPAD28
TP3
TP3
CPU_RSVD05
B2
RSVD#B2
TPAD28
TPAD28
TP8
TP8
C3
RSVD#C3
TPAD28
TPAD28
TP4
TP4
D2
layout note:Zo =55
ohm , 0.5" MAX for
GTLREF
RSVD#D2
TPAD28
TPAD28
TP12
TP12
layout note : Change R237 to 649 ohm if using XTP to ITP adapter
D22
RSVD#D22
3D3V_S0
TPAD28
TPAD28
TP6
TP6
D3
RSVD#D3
TPAD28
TPAD28
TP11
TP11
F6
RSVD#F6
R29
R29
TPAD28
TPAD28
TP2
TP2
B1
KEY_NC
XDP_DBRESET#
1
2
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1D05V_S0
original value:BGA479-SKT6-GPU1
XDP_TDI
1
2
R31
R31
54D9R2F-L1-GP
54D9R2F-L1-GP
B
XDP_TMS
B
1
2
R30
R30
54D9R2F-L1-GP
54D9R2F-L1-GP
XDP_TDO
XDP_BPM#5
1
2
R33
R33
54D9R2F-L1-GP
54D9R2F-L1-GP
1
2
R55
R55
54D9R2F-L1-GP
54D9R2F-L1-GP
XDP_TRST#
XDP_TCK
1
2
R28
R28
51R2F-2-GP
51R2F-2-GP
1D05V_S0
1
2
R42
R42
54D9R2F-L1-GP
54D9R2F-L1-GP
R123
56R2J-4-GP
R123
56R2J-4-GP
DY
DY
DY
Q8
MMBT3904WT1G-GP
DY
CPU_PROCHOT#
E
C
OCP#
20
Q8
MMBT3904WT1G-GP
A
A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Wednesday, May 23, 2007
Wednesday, May 23, 2007
Wednesday, May 23, 2007
Sheet
Sheet
Sheet
of
of
of
41
41
41
4
4
4
5
4
3
2
1
5
4
3
2
1
7
H_D#[0..63]
VCC_CORE_S0
VCC_CORE_S0
U53B
U53B
2 OF 4
2 OF 4
U53C
U53C
3 OF 4
3 OF 4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
E22
Y22
D0#
D32#
F24
AB24
A7
AB20
D1#
D33#
VCC
VCC
E26
V24
A9
AB7
D2#
D34#
VCC
VCC
G22
V26
A10
AC7
D3#
D35#
VCC
VCC
F23
V23
A12
AC9
D
D4#
D36#
VCC
VCC
D
G25
T22
A13
AC12
D5#
D37#
VCC
VCC
E25
U25
A15
AC13
D6#
D38#
VCC
VCC
E23
U23
A17
AC15
D7#
D39#
VCC
VCC
K24
Y25
A18
AC17
D8#
D40#
VCC
VCC
G24
W22
A20
AC18
D9#
D41#
VCC
VCC
J24
Y23
B7
AD7
D10#
D42#
VCC
VCC
J23
W24
B9
AD9
D11#
D43#
VCC
VCC
H22
W25
B10
AD10
D12#
D44#
VCC
VCC
F26
AA23
B12
AD12
D13#
D45#
VCC
VCC
K22
AA24
B14
AD14
D14#
D46#
VCC
VCC
H23
AB25
B15
AD15
D15#
D47#
VCC
VCC
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DSTBN#2
H_DSTBP#2
H_DINV#2
J26
Y26
B17
AD17
7
H_DSTBN#0
DSTBN0#
DSTBN2#
H_DSTBN#2
7
VCC
VCC
H26
AA26
B18
AD18
7
H_DSTBP#0
DSTBP0#
DSTBP2#
H_DSTBP#2
7
VCC
VCC
H25
U22
B20
AE9
7
H_DINV#0
H_DINV#2
7
DINV0#
DINV2#
VCC
VCC
C9
AE10
VCC
VCC
C10
AE12
VCC
VCC
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
N22
AE24
C12
AE13
D16#
D48#
VCC
VCC
K25
AD24
C13
AE15
D17#
D49#
VCC
VCC
P26
AA21
C15
AE17
D18#
D50#
VCC
VCC
R23
AB22
C17
AE18
D19#
D51#
VCC
VCC
L23
AB21
C18
AE20
D20#
D52#
VCC
VCC
M24
AC26
D9
AF9
D21#
D53#
VCC
VCC
L22
AD20
D10
AF10
D22#
D54#
VCC
VCC
M23
AE22
D12
AF12
D23#
D55#
VCC
VCC
P25
AF23
D14
AF14
D24#
D56#
VCC
VCC
P23
AC25
D15
AF15
D25#
D57#
VCC
VCC
P22
AE21
D17
AF17
D26#
D58#
VCC
VCC
T24
AD21
D18
AF18
D27#
D59#
VCC
VCC
1D05V_S0
R24
AC22
E7
AF20
D28#
D60#
VCC
VCC
C
C
L25
AD23
E9
D29#
D61#
VCC
R113
R113
0R0402-PAD
0R0402-PAD
T25
AF22
E10
G21
1
2
D30#
D62#
VCC
VCCP
N25
AC23
E12
V6
1
R100
R100
2
0R0402-PAD
0R0402-PAD
D31#
D63#
VCC
VCCP
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_DSTBN#3
H_DSTBP#3
H_DINV#3
TC15
TC15
L26
AE25
E13
J6
7
H_DSTBN#1
DSTBN1#
DSTBN3#
H_DSTBN#3
7
VCC
VCCP
M26
AF24
E15
K6
7
H_DSTBP#1
H_DSTBP#3
7
DSTBP1#
DSTBP3#
VCC
VCCP
N24
AC20
E17
M6
7
H_DINV#1
H_DINV#3
7
DINV1#
DINV3#
VCC
VCCP
E18
J21
VCC
VCCP
V_CPU_GTLREF
COMP0
COMP1
COMP2
COMP3
DY
DY
AD26
R26
1
2
E20
K21
GTLREF
COMP0
VCC
VCCP
TPAD28
TPAD28
TP13
TP13
TEST1
TEST2
MISC
MISC
R131
R131
27D4R2F-L1-GP
27D4R2F-L1-GP
C23
U26
1
2
F7
M21
TEST1
COMP1
VCC
VCCP
TPAD28
TPAD28
TP16
TP16
R132
R132
54D9R2F-L1-GP
54D9R2F-L1-GP
D25
AA1
1
2
F9
N21
TEST2
COMP2
VCC
VCCP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
TPAD28
TPAD28
TP14
TP14
TEST3
C24
Y1
R84
R84
1
2
27D4R2F-L1-GP
27D4R2F-L1-GP
F10
N6
TEST3
COMP3
VCC
VCCP
C154
C154
TEST4
R83
R83
54D9R2F-L1-GP
54D9R2F-L1-GP
1
2
AF26
F12
R21
TEST4
VCC
VCCP
TPAD28
TPAD28
TP1
TP1
TEST5
TEST6
H_DPRSTP#
H_DPWR#
H_CPUSLP#
PSI#
AF1
E5
F14
R6
H_DPRSTP#
7,19
TEST5
DPRSTP#
VCC
VCCP
TPAD28
TPAD28
TP15
TP15
H_DPSLP#
DY
DY
A26
B5
F15
T21
H_DPSLP#
19
TEST6
DPSLP#
VCC
VCCP
D24
SB
F17
T6
DPWR#
H_DPWR#
7
VCC
VCCP
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
B22
D6
F18
V21
3
CPU_BSEL0
BSEL0
PWRGOOD
H_PWRGOOD
19
VCC
VCCP
1D5V_S0
layout note:
place C3 near
PIN B26
B23
D7
F20
W21
3
CPU_BSEL1
BSEL1
SLP#
H_CPUSLP#
7
VCC
VCCP
C21
AE6
AA7
3
CPU_BSEL2
BSEL2
PSI#
PSI#
35
VCC
AA9
B26
C156
VCC
VCCA
AA10
C26
VCC
VCCA
AA12
VCC
CPU_VID[0..6]
35
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
C161
SC10U10V5ZY-1GP
AA13
AD6
VCC
VID0
AA15
AF5
VCC
VID1
PLACE C173 close to the TEST4 PIN,
make sure TEST3,TEST4,TEST5 trace
routing is reference to GND and
away other noisy signals
AA17
AE5
VCC
VID2
AA18
AF4
VCC
VID3
AA20
AE3
VCC
VID4
AB9
AF3
VCC
VID5
AC10
AE2
VCC
VID6
AB10
VCC
B
Length match within
25 mils . The trace
width/space/other is
20/7/25 .
B
AB12
VCC
Resistor Placed
within 0.5" of CPU
pin. Trace should
be at least 25 mils
away from any other
toggling signal .
COMP[0,2] trace
width is 18 mils.
COMP[1,3] trace
width is 4 mils .
AB14
AF7
VCC_SENSE
VCC
VCCSENSE
VCC_SENSE
35
AB15
VCC
AB17
VCC
VSS_SENSE
AB18
AE7
VCC
VSSSENSE
VSS_SENSE
35
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VCC_SENSE
1
2
VCC_CORE_S0
166
0
1
1
R99
R99
100R2F-L1-GP-U
100R2F-L1-GP-U
VSS_SENSE
1 2
R98 100R2F-L1-GP-U
R98 100R2F-L1-GP-U
200
0
1
0
Close to CPU pin
within 500mils
1D05V_S0
Close to CPU
pin AD26
Z0=55 ohm
with in
500mils .
R352
1KR2F-3-GP
<Core Design>
<Core Design>
<Core Design>
A
A
V_CPU_GTLREF
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R353
2KR2F-3-GP
Title
Title
Title
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Friday, May 18, 2007
Friday, May 18, 2007
Friday, May 18, 2007
Sheet
Sheet
Sheet
of
of
of
41
41
41
5
5
5
5
4
3
2
1
[ Pobierz całość w formacie PDF ]
zanotowane.pl doc.pisz.pl pdf.pisz.pl chiara76.opx.pl
5
4
3
2
1
Pamirs UMA Block Diagram
SYSTEM DC/DC
TPS51120
INPUTS
OUTPUTS
5V_S3
Project code : 91.4S401.001
PCB P/N :06228
Revision : SB
Intel CPU
DCBATOUT
3V_AUX_S5
CLK GEN
Meron 2M/4M SV
FSB:667 or 800 MHz
SYSTEM DC/DC
D
D
MAX8743
ICS9LPRS355AKLFT-GP
4,5,6
INPUTS
OUTPUTS
3
CRT
RGB CRT
15
1D5V_S0
Host BUS
533/667MHz
DCBATOUT
1D8V_S3
LVDS
LCD
SYSTEM DC/DC
16
DDRII
533/667
ISL6269CRZ
Slot 0
Crestline-GM/GML
AGTL+ CPU I/F
INTEGRATED GRAHPICS
DDRII 667 Channel A
13
INPUTS
DCBATOUT
OUTPUTS
1D05V_S0
TVOUT
DDR I/F
SVIDEO
15
DDRII
533/667
Slot 1
DDR II 667 Channel B
PCIE x 16
LVDS, CRT I/F
MAXIM CHARGER
14
7,8,9,10,11,12
MAX8725
INPUTS
OUTPUTS
C
1394
1394
DMI I/F
100MHz
C
BT+
Ricoh
R5C832
25
CAMERA
DCBATOUT
18V 3.0A
32
5V 100mA
SD/SDIO/MMC
MS/MS Pro/xD
PCI
CardReader
INTEL
BLUE
TOOTH
25
24,25
CPU DC/DC
32
MAX8736ETL
ICH8-M
USB x 3
USB 2.0
INPUTS
OUTPUTS
23
10/100 NIC
LCI
10 USB 2.0/1.1 ports
(10/100/1000Mb)
RJ45
CONN
Marvell 88E8039
VCC_CORE
27
ETHERNET
SATA
HDD
DCBATOUT
28
High Definition Audio
23
0.844~1.3V
44A
ATA 66/100
PATA
ODD
AMOM
MODEM
ACPI 1.1
LPC I/F
23
PCB LAYER
B
RJ11
CONN
B
HD Audio
TPM
SLB9635T
34
29
CX20548
PCI/PCI BRIDGE
LPC Bus
L1:
Signal 1
18,19,20,21
INTERNAL
ARRAY MIC
L2:
GND
HD AUDIO
CODEC
CX20549-12Z
L3:
Signal 2
MIC IN
L4:
Signal 3
KBC
PCIE+USB 2.0
LINE OUT
29
ENE KB3910SF
L5:
VCC
Signal 4
Ricoh
R5538
31
L6:
SPDIF
28
Flash ROM
1MB
OP AMP
Thermal
& Fan
33
Mini-Card
Mini-Card
Capacity
Button
Touch
Pad
Int.
KB
APA2031
New Card
CIR
802.11a/b/g
WWAN
30
A
<Core Design>
<Core Design>
<Core Design>
A
G792
28
26
26
32
32
32
22
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2CH
SPEAKER
DOCK
10/100
Ethernet
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
CRT
MIC IN
LINE OUT
S/PDIF
TVOUT
CIR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Friday, May 18, 2007
Friday, May 18, 2007
Friday, May 18, 2007
Sheet
Sheet
Sheet
1
1
1
of
of
of
41
41
41
5
4
3
2
1
A
B
C
D
E
INTEL ICH8-M STRAP PIN
19,21
+RTCVCC
+RTCVCC
1D05V_S0
1D25V_S0
1D2V_LAN_S5
4,5,6,7,9,10,11,19,21,38,41
1D05V_S0
3,7,10,21,38
1D25V_S0
Signal
Usage/When Sampled
Comment
XOR Chain Entrance Strap
27
1D2V_LAN_S5
HDA_SDOUT
XOR Chain Entrance/
PCIE Port Config 1 bit1,
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3
pulled low at rising edge of PWROK.When TP3 not
pulled low at rising edge of PWROK,sets bit1 of
RPC.PC(Config Registers:offset 224h)
ICH_RSVD
tp3
AZ_DOUT_ICH
Description
28
1D5V_NEW_S0
1D5V_NEW_S0
0
0
RSVD
4
4
0
1
Enter XOR Chain
5,10,17,19,20,21,26,28,37,38,41
1D5V_S0
1D5V_S0
1
0
Normal Operation(default)
1
1
Set PCIE port cofig bit1
7,10,11,13,14,37,38,41
1D8V_S3
1D8V_S3
HDA_SYNC
PCIE Port Config 1 bit0,
Rising Edge of PWROK.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
27,28
2D5V_LAN_S5
2D5V_LAN_S5
GNT2#
PCIE Port Config 2 bit0,
Rising Edge of PWROK.
Sets bit2 of RPC.PC(Config Registers:Offset 224h)
29,30
3D3V_AUD_S0
3D3V_AUD_S0
19,31,32,33,36,39,40
3D3V_AUX_S5
3D3V_AUX_S5
3D3V_LAN_S5
GPIO20
Reserved
Weak Internal PULL-DOWN.NOTE:This signal should
not be pull HIGH.
27,28
3D3V_LAN_S5
3,4,7,9,10,11,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,35,36,41
3D3V_S0
3D3V_S0
Sampled low:Top-Block Swap mode(inverts A16 for all
cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
A16 swap override strap
low = A16 swap override enable
high = default
GNT3#
Top-Block Swap Override.
Rising Edge of PWROK.
17,18,20,21,22,26,27,28,29,31,34,36,39,41
3D3V_S5
3D3V_S5
PCI_GNT#3
22,29,31,34,36
5V_AUX_S5
5V_AUX_S5
BOOT BIOS Strap
16,23,32,33,34,36,37,38
5V_S3
5V_S3
PCI_GNT#0
SPI_CS#1
BOOT BIOS Location
SPI
GNT0#
SPI_CS1#
Boot BIOS Destination
Selection.
Rising Edge of PWROK.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
15,16,17,20,21,22,23,26,29,30,31,32,33,34,35,41
5V_S0
5V_S0
0
1
1
0
PCI
LPC(Default)
16,21,34,37,38
5V_S5
5V_S5
AD+
1
1
Integrated VccSus1_05
VccSus1_5 and VccCL1_5
VRM Enable/Disable.Always
sampled.
17,39,40,41
AD+
Enables integrated VccSus1_05,VccSus1_5 and
VccCL1_5 VRM when sampled high
integrated VccSus1_05,VccSus1_5,VccCL1_5
INTVRMEN
16,17,34,35,36,37,38,39,41
DCBATOUT
DCBATOUT
SM_INTVRMEN
integrated VccLan1_05VccCL1_05
High=Enable Low=Disable
13,14,38,41
DDR_VREF_S0
DDR_VREF_S0
3
3
Integrated VccLAN1_05
VccCL1_05 VRM enable
/Disable. Always sampled.
Enables integrated VccLAN1_05,VccCL1_05 VRM
when sampled high
7,13,14,38
DDR_VREF_S3
DDR_VREF_S3
LAN100_SLP
LAN100_SLP
High=Enable Low=Disable
22,31,33,39
KBC_3D3V_AUX
KBC_3D3V_AUX
16
VCC_CORE_S0
LCDVDD_S0
LCDVDD_S0
VCC_CORE_S0
SATALED#
PCIE LAN REVERSAL.Rising
Edge of PWROK.
This signal has weak internal pull-up.
set bit27 of MPC.LR(Device28:Function0:Offset D8)
DEFAULE HIGH
5,6,35
No Reboot Strap
If sampled high, the system is strapped to the
"No Reboot" mode(ICH8M will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.(Offset:3410h:bit5)
SPKR
No Reboot.
Rising Edge of PWROK.
SPKR
LOW = Defaule
High=No Reboot
TP3
XOR Chain Entrance.
Rising Edge of PWROK.
This signal should not be pull low unless using
XOR Chain testing.
INTEL ICH8-M INTEGRATED
PULL-UPS and PULL-DOWNS
SIGNAL
Internal Pull-Up.If sampled low,the Flash Descriptor
Security will be overidden.if high,the Security
measures defined in the Flash Descriptor will be in
effect.
GPIO33/
HDA_DOCK_EN#
Flash Descriptor Security
Override Strap
Rising Edge of PWROK.
8.2K PULL HIGH
This should only be used in manufacturing
environments
Resistor Type/Value
HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
PULL-DOWN 20K
NONE
2
2
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
INTEL CRESTLINE STRAP PIN
PULL-UP 20K
CFG Strap
LOW 0
HIGH 1
PULL-DOWN 20K
CFG 5
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
º
DMI X 2
DMI X 4
CFG 8
LAN_RXD[2:0]
º
Low Power PCI Express
Normal
Low Power mode
CFG 9
LDRQ[0]
º
PCI Express Graphics
Lane Reversal
Lane Reversal
Normal Mode(Lanes
number in order)
LDRQ[1]/GPIO23
CFG 16
º
FSB Dynamic ODT
Disabled
Enabled
PME#
PWRBTN#
SATALED#
CFG 19
º
DMI Lane Reserved
Normal Operation
Reserved Lane
CFG 20
Only PCIE or SDVO
is operation
PCIE and SDVO are
operation simultaneous
º
Concurrent SDVO/PCIE
SDVO_CTRL_DATA
SDVO Present
NO SDVO Card
Present
SDVO Card Present
SPI_CS1#
º
SPI_CLK
<Core Design>
<Core Design>
<Core Design>
CFG 12
XOR/ALL-Z
SPI_MOSI
SPI_MISO
TACH_[3:0]
1
1
CFG 13
LL(00)
LH(01)
HL(10)
HH(11)
Reserved
XOR Mode Enabled
All Z Mode Enabled
Normal Operation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SPKR
PULL-DOWN 20K
Title
Title
Title
TP[3]
PULL-UP 20K
Table of Content
Table of Content
Table of Content
USB[9:0][P,N]
CL_RST#
PULL-DOWN 15K
TBD
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Tuesday, May 22, 2007
Tuesday, May 22, 2007
Tuesday, May 22, 2007
Sheet
Sheet
Sheet
2
2
2
of
of
of
41
41
41
A
B
C
D
E
5
4
3
2
1
3D3V_S0
3D3V_S0_CK505
L11
L11
2/12
3D3V_S0_CK505
3D3V_S0_CK505_IO
2/12
1
2
0R0603-PAD
0R0603-PAD
C484
C195
C448
C448
C439
C442
C442
C475
C440
C445
DY
DY
DY
DY
X1
X1
CLK_XTAL_IN
CLK_XTAL_OUT
1
2
X-14D31818M-40GP
X-14D31818M-40GP
D
D
C186
SC27P50V2JN-2-GP
C185
SC27P50V2JN-2-GP
U21
U21
2/12
1D25V_S0
R650
R650
3D3V_S0
CLK_CPU_BCLK1
RN29
RN29
SRN0J-6-GP
SRN0J-6-GP
1
2
61
1
2
4
CLK_CPU_BCLK
4
CPUT0
3D3V_S0_CK505_IO
CLK_CPU_BCLK1#
CLK_MCH_BCLK1
60
3
CLK_CPU_BCLK#
4
CPUC0
DUMMY-R3
DUMMY-R3
CLK_XTAL_IN
L36
L36
3
58
RN32
RN32
1
2
4
SRN0J-6-GP
SRN0J-6-GP
CLK_MCH_BCLK
7
X1
CPUT1_F
C190
C190
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
CLK_XTAL_OUT
CLK_MCH_BCLK1#
1
2
2
57
3
CLK_MCH_BCLK#
7
X2
CPUC1_F
0R0603-PAD
0R0603-PAD
1
2
54
CLK_CPU_XDP1
CLK_CPU_XDP1#
TP103
TP103
CPUT2_ITP/SRCT8
C212
C441
C466
C459
C459
C465
C200
C206
53
TP104
TP104
2/12
CPUC2_ITP/SRCC8
C446
FSA
1
2
17
20
CLK_48M_ICH
USB_48MHZ/FSLA
12/12
DY
DY
R159
R159
33R2J-2-GP
33R2J-2-GP
CLK_PCIE_LAN1
CLK_PCIE_LAN1#
RN36
RN36
SRN0J-6-GP
SRN0J-6-GP
51
1
2
4
SRCT7/CR#_F
CLK_PCIE_LAN
27
50
3
CLK_PCIE_LAN#
27
SRCC7/CR#_E
45
20
H_STP_PCI#
PCI_STOP#
CLK_PCIE_MINI1_1
RN44
RN44
SRN0J-6-GP
SRN0J-6-GP
44
48
1
2
4
CLK_PCIE_MINI1
26
20
H_STP_CPU#
CPU_STOP#
SRCT6
CLK_PCIE_MINI1_1#
47
3
CLK_PCIE_MINI1#
26
SRCC6
CLK_PCIE_NEW1
41
2
3
4
CLK_PCIE_NEW
28
SRCT10
CLK_PCIE_NEW1#
7
42
1
CLK_PCIE_NEW#
28
13,14,20
ICH_SMBDATA
ICH_SMBCLK
SCLK
SRCC10
RN42
RN42
SRN0J-6-
G
P
SRN0J-6-GP
6
1
2
13,14,20
SDATA
3D3V_S0
40
R184
R184
10KR2J-3-GP
10KR2J-3-GP
SRCT11/CR#_H
NEWCARD_CLKREQ#
28
R183
R183
63
39
1
2
20
CK_PWRGD
CK_PWRGD/PD#
SRCC11/CR#_G
C
C
12/18
DY
DY
10KR2J-3-GP
10KR2J-3-GP
CLK_PCIE_MINI2_1
37
2
3
4
SRCT9
CLK_PCIE_MINI2
26
12/18
38
CLK_PCIE_MINI2_1#
1
CLK_PCIE_MINI2#
26
SRCC9
RN41
RN41
SRN0J-6-GP
SRN0J-6-GP
8
20
CLKSATAREQ#
PCI0/CR#_A
CLK_MCH_3GPLL1
10
34
2
3
4
CLK_MCH_3GPLL
7
7
CLKREQ#_B
PCI1/CR#_B
SRCT4
R143
R143
33R2J-2-GP
33R2J-2-GP
PCI2_TME
CLK_MCH_3GPLL1#
1
2
11
35
1
CLK_MCH_3GPLL#
7
33
PCLK_FWH
PCI2/TME
SRCC4
RN40
RN40
SRN0J-6-GP
SRN0J-6-GP
R150
R150
1
DY
DY
2
33R2J-2-GP
33R2J-2-GP
12
34
CLK_PCI_TCG
PCI3
R151
R151
33R2J-2-GP
33R2J-2-GP
27_SEL
CLK_PCIE_ICH1
1
2
13
31
2
3
4
31
PCLK_KBC
CLK_PCIE_ICH
20
PCI4/27_SELECT
SRCT3/CR#_C
R153
R153
33R2J-2-GP
33R2J-2-GP
ITP_EN
CLK_PCIE_ICH1#
1
2
14
32
1
18
CLK_PCI_ICH
CLK_PCIE_ICH#
20
PCI_F5/ITP_EN
SRCC3/CR#_D
RN39
RN39
SRN0J-6-GP
SRN0J-6-GP
R152
R152
33R2J-2-GP
33R2J-2-GP
1
2
24
PCLK_PCM
CLK_PCIE_SATA1
CLK_PCIE_SATA1
28
2
3
4
CLK_PCIE_SATA
19
SRCT2/SATAT
CLK_PCIE_SATA1#
CLK_PCIE_SATA1#
29
1
R382
R382
CLK_PCIE_SATA#
19
SRCC2/SATAC
RN38
RN38
SRN0J-6-GP
SRN0J-6-GP
FSB
64
FSLB/TEST_MODE
1
2
FSC
5
01/31
10/24
20
CLK_14M_ICH
REF0/FSLC/TEST_SEL
MCH_SSCDREFCLK1
24
2
3
4
MCH_SSCDREFCLK
7
27MHZ_NONSS/SRCT1/SE1
MCH_SSCDREFCLK1#
55
25
1
MCH_SSCDREFCLK#
7
33R2J-2-GP
33R2J-2-GP
NC#55
27MHZ_SS/SRCC1/SE2
RN33
RN33
SRN0J-6-GP
SRN0J-6-GP
20
CLK_MCH_DREFCLK1
2
3
4
SRCT0/DOTT_96
CLK_MCH_DREFCLK
7
3D3V_S0_CK505
01/31
CLK_MCH_DREFCLK1#
21
1
CLK_MCH_DREFCLK#
7
SRCC0/DOTC_96
RN31
RN31
SRN0J-6-GP
SRN0J-6-GP
DY
R385
10KR2J-3-GP
ICS9LPRS355AKLFT-GP
ICS9LPRS355AKLFT-GP
12/20
PCI2_TME
B
B
3D3V_S0_CK505
R386
10KR2J-3-GP
R386
10KR2J-3-GP
DY
DY
R141
10KR2J-3-GP
R141
10KR2J-3-GP
FS_C FS_B FS_A CPU
1 0 1 100M
0 0 1 133M
0 1 0 200M
0 1 1 166M
DY
DY
3D3V_S0_CK505
27_SEL
R142
10KR2J-3-GP
R379
10KR2J-3-GP
27_SEL PIN 20 PIN 21 PIN 24 PIN 25
0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100
1 SRCT0 SRCC0 27M_NSS 27M_SS
ITP_EN Output
0 SRC8
1 CPU_ITP
FSC
1
2
5
CPU_BSEL2
ITP_EN
R381
R381
10KR2J-3-GP
10KR2J-3-GP
1
2
FSB
FSA
5
CPU_BSEL1
R163
R163
0R0402-PAD
0R0402-PAD
R378
10KR2J-3-GP
R378
10KR2J-3-GP
1
2
5
CPU_BSEL0
DY
DY
R160
R160
2K2R2J-2-GP
2K2R2J-2-GP
R149
R149
1KR2J-1-GP
1KR2J-1-GP
1
2
MCH_CLKSEL0
7
R134
R134
1KR2J-1-GP
1KR2J-1-GP
1
2
MCH_CLKSEL1
7
<Variant Name>
<Variant Name>
<Variant Name>
A
A
R377
R377
1KR2J-1-GP
1KR2J-1-GP
1
2
MCH_CLKSEL2
7
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Design Note:
1. All of Input pin didn't have internal pull up resistor.
2. Clock Request (CR) function are enable by registers.
3. CY28548 integrated serial resistor of differential clock,
so put 0 ohm serial resistor in the schematic.
Title
Title
Title
Clock generator CY28548
Clock generator CY28548
Clock generator CY28548
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Monday, May 21, 2007
Monday, May 21, 2007
Monday, May 21, 2007
Sheet
Sheet
Sheet
3
3
3
of
of
of
41
41
41
5
4
3
2
1
5
4
3
2
1
7
H_A#[3..35]
U53A
U53A
1 OF 4
1 OF 4
1D05V_S0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_ADS#
H_BNR#
H_BPRI#
J4
H1
H_ADS#
7
A3#
ADS#
L5
E2
A4#
BNR#
H_BNR#
7
L4
G5
A5#
BPRI#
H_BPRI#
7
K5
A6#
H_DEFER#
D
M3
H5
D
H_DEFER#
7
A7#
DEFER#
H_DRDY#
R114
56R2J-4-GP
N2
F21
A8#
DRDY#
H_DRDY#
7
J1
E1
H_DBSY#
A9#
DBSY#
H_DBSY#
7
N3
A10#
H_BR0#
P5
F1
H_BR0#
7
A11#
BR0#
P2
A12#
L2
D20
H_IERR#
A13#
IERR#
H_INIT#
P4
B3
A14#
INIT#
H_INIT#
19
P1
A15#
H_LOCK#
R1
H4
H_LOCK#
7
A16#
LOCK#
M1
7
H_ADSTB#0
ADSTB0#
H_RESET#
C1
RESET#
H_RESET#
7
H_REQ#0
H_REQ#2
H_REQ#3
H_RS#0
K3
F3
7
H_REQ#0
REQ0#
RS0#
H_RS#0
7
H_REQ#1
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
H2
F4
7
H_REQ#1
REQ1#
RS1#
H_RS#1
7
K2
G3
7
H_REQ#2
REQ2#
RS2#
H_RS#2
7
J3
G2
7
H_REQ#3
REQ3#
TRDY#
H_TRDY#
7
H_REQ#4
L1
7
H_REQ#4
REQ4#
G6
HIT#
H_HIT#
7
H_A#17
Y2
E4
A17#
HITM#
H_HITM#
7
H_A#18
H_A#19
U5
A18#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
TP68
TP68
R3
AD4
A19#
BPM0#
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
TP91
TP91
2/12
W6
AD3
A20#
BPM1#
U4
AD1
TP93
TP93
A21#
BPM2#
TP101
TP101
Y5
AC4
A22#
BPM3#
TP102
TP102
U1
AC2
A23#
PRDY#
R4
AC1
A24#
PREQ#
T5
AC5
A25#
TCK
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
T3
AA6
A26#
TDI
W2
AB3
A27#
TDO
W5
AB5
A28#
TMS
Y4
AB6
A29#
TRST#
U2
C20
A30#
DBR#
XDP_DBRESET#
20
V4
A31#
H_A#32
W3
A32#
CPU_PROCHOT#
35
THERMAL
THERMAL
H_A#33
AA4
C
A33#
C
H_A#34
H_A#35
AB2
1
2
A34#
1D05V_S0
R122
R122
68R3J-GP
68R3J-GP
AA3
D21
A35#
PROCHOT#
H_ADSTB#1
H_THERMDA
H_THERMDC
V1
A24
7
H_ADSTB#1
ADSTB1#
THRMDA
H_THERMDA
22
B25
THRMDC
H_THERMDC
22
H_A20M#
H_IGNNE#
A6
19
H_A20M#
A20M#
H_FERR#
H_THERMTRIP#
A5
C7
19
H_FERR#
FERR#
THERMTRIP#
H_THERMTRIP#
7,19
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
C4
19
H_IGNNE#
IGNNE#
D5
19
H_STPCLK#
STPCLK#
HCLK
HCLK
CLK_CPU_BCLK
CLK_CPU_BCLK#
C6
A22
19
H_INTR
CLK_CPU_BCLK
3
LINT0
BCLK0
B4
A21
19
H_NMI
CLK_CPU_BCLK#
3
LINT1
BCLK1
A3
19
H_SMI#
SMI#
TPAD28
TPAD28
TP9
TP9
CPU_RSVD01
CPU_RSVD03
M4
RSVD#M4
TPAD28
TPAD28
TP10
TP10
CPU_RSVD02
CPU_RSVD04
CPU_RSVD06
CPU_RSVD07
CPU_RSVD08
CPU_RSVD09
CPU_RSVD10
CPU_RSVD11
N5
RSVD#N5
TPAD28
TPAD28
TP5
TP5
T2
RSVD#T2
TPAD28
TPAD28
TP7
TP7
V3
RSVD#V3
TPAD28
TPAD28
TP3
TP3
CPU_RSVD05
B2
RSVD#B2
TPAD28
TPAD28
TP8
TP8
C3
RSVD#C3
TPAD28
TPAD28
TP4
TP4
D2
layout note:Zo =55
ohm , 0.5" MAX for
GTLREF
RSVD#D2
TPAD28
TPAD28
TP12
TP12
layout note : Change R237 to 649 ohm if using XTP to ITP adapter
D22
RSVD#D22
3D3V_S0
TPAD28
TPAD28
TP6
TP6
D3
RSVD#D3
TPAD28
TPAD28
TP11
TP11
F6
RSVD#F6
R29
R29
TPAD28
TPAD28
TP2
TP2
B1
KEY_NC
XDP_DBRESET#
1
2
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1D05V_S0
original value:BGA479-SKT6-GPU1
XDP_TDI
1
2
R31
R31
54D9R2F-L1-GP
54D9R2F-L1-GP
B
XDP_TMS
B
1
2
R30
R30
54D9R2F-L1-GP
54D9R2F-L1-GP
XDP_TDO
XDP_BPM#5
1
2
R33
R33
54D9R2F-L1-GP
54D9R2F-L1-GP
1
2
R55
R55
54D9R2F-L1-GP
54D9R2F-L1-GP
XDP_TRST#
XDP_TCK
1
2
R28
R28
51R2F-2-GP
51R2F-2-GP
1D05V_S0
1
2
R42
R42
54D9R2F-L1-GP
54D9R2F-L1-GP
R123
56R2J-4-GP
R123
56R2J-4-GP
DY
DY
DY
Q8
MMBT3904WT1G-GP
DY
CPU_PROCHOT#
E
C
OCP#
20
Q8
MMBT3904WT1G-GP
A
A
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Wednesday, May 23, 2007
Wednesday, May 23, 2007
Wednesday, May 23, 2007
Sheet
Sheet
Sheet
of
of
of
41
41
41
4
4
4
5
4
3
2
1
5
4
3
2
1
7
H_D#[0..63]
VCC_CORE_S0
VCC_CORE_S0
U53B
U53B
2 OF 4
2 OF 4
U53C
U53C
3 OF 4
3 OF 4
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
E22
Y22
D0#
D32#
F24
AB24
A7
AB20
D1#
D33#
VCC
VCC
E26
V24
A9
AB7
D2#
D34#
VCC
VCC
G22
V26
A10
AC7
D3#
D35#
VCC
VCC
F23
V23
A12
AC9
D
D4#
D36#
VCC
VCC
D
G25
T22
A13
AC12
D5#
D37#
VCC
VCC
E25
U25
A15
AC13
D6#
D38#
VCC
VCC
E23
U23
A17
AC15
D7#
D39#
VCC
VCC
K24
Y25
A18
AC17
D8#
D40#
VCC
VCC
G24
W22
A20
AC18
D9#
D41#
VCC
VCC
J24
Y23
B7
AD7
D10#
D42#
VCC
VCC
J23
W24
B9
AD9
D11#
D43#
VCC
VCC
H22
W25
B10
AD10
D12#
D44#
VCC
VCC
F26
AA23
B12
AD12
D13#
D45#
VCC
VCC
K22
AA24
B14
AD14
D14#
D46#
VCC
VCC
H23
AB25
B15
AD15
D15#
D47#
VCC
VCC
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_DSTBN#2
H_DSTBP#2
H_DINV#2
J26
Y26
B17
AD17
7
H_DSTBN#0
DSTBN0#
DSTBN2#
H_DSTBN#2
7
VCC
VCC
H26
AA26
B18
AD18
7
H_DSTBP#0
DSTBP0#
DSTBP2#
H_DSTBP#2
7
VCC
VCC
H25
U22
B20
AE9
7
H_DINV#0
H_DINV#2
7
DINV0#
DINV2#
VCC
VCC
C9
AE10
VCC
VCC
C10
AE12
VCC
VCC
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
N22
AE24
C12
AE13
D16#
D48#
VCC
VCC
K25
AD24
C13
AE15
D17#
D49#
VCC
VCC
P26
AA21
C15
AE17
D18#
D50#
VCC
VCC
R23
AB22
C17
AE18
D19#
D51#
VCC
VCC
L23
AB21
C18
AE20
D20#
D52#
VCC
VCC
M24
AC26
D9
AF9
D21#
D53#
VCC
VCC
L22
AD20
D10
AF10
D22#
D54#
VCC
VCC
M23
AE22
D12
AF12
D23#
D55#
VCC
VCC
P25
AF23
D14
AF14
D24#
D56#
VCC
VCC
P23
AC25
D15
AF15
D25#
D57#
VCC
VCC
P22
AE21
D17
AF17
D26#
D58#
VCC
VCC
T24
AD21
D18
AF18
D27#
D59#
VCC
VCC
1D05V_S0
R24
AC22
E7
AF20
D28#
D60#
VCC
VCC
C
C
L25
AD23
E9
D29#
D61#
VCC
R113
R113
0R0402-PAD
0R0402-PAD
T25
AF22
E10
G21
1
2
D30#
D62#
VCC
VCCP
N25
AC23
E12
V6
1
R100
R100
2
0R0402-PAD
0R0402-PAD
D31#
D63#
VCC
VCCP
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_DSTBN#3
H_DSTBP#3
H_DINV#3
TC15
TC15
L26
AE25
E13
J6
7
H_DSTBN#1
DSTBN1#
DSTBN3#
H_DSTBN#3
7
VCC
VCCP
M26
AF24
E15
K6
7
H_DSTBP#1
H_DSTBP#3
7
DSTBP1#
DSTBP3#
VCC
VCCP
N24
AC20
E17
M6
7
H_DINV#1
H_DINV#3
7
DINV1#
DINV3#
VCC
VCCP
E18
J21
VCC
VCCP
V_CPU_GTLREF
COMP0
COMP1
COMP2
COMP3
DY
DY
AD26
R26
1
2
E20
K21
GTLREF
COMP0
VCC
VCCP
TPAD28
TPAD28
TP13
TP13
TEST1
TEST2
MISC
MISC
R131
R131
27D4R2F-L1-GP
27D4R2F-L1-GP
C23
U26
1
2
F7
M21
TEST1
COMP1
VCC
VCCP
TPAD28
TPAD28
TP16
TP16
R132
R132
54D9R2F-L1-GP
54D9R2F-L1-GP
D25
AA1
1
2
F9
N21
TEST2
COMP2
VCC
VCCP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
TPAD28
TPAD28
TP14
TP14
TEST3
C24
Y1
R84
R84
1
2
27D4R2F-L1-GP
27D4R2F-L1-GP
F10
N6
TEST3
COMP3
VCC
VCCP
C154
C154
TEST4
R83
R83
54D9R2F-L1-GP
54D9R2F-L1-GP
1
2
AF26
F12
R21
TEST4
VCC
VCCP
TPAD28
TPAD28
TP1
TP1
TEST5
TEST6
H_DPRSTP#
H_DPWR#
H_CPUSLP#
PSI#
AF1
E5
F14
R6
H_DPRSTP#
7,19
TEST5
DPRSTP#
VCC
VCCP
TPAD28
TPAD28
TP15
TP15
H_DPSLP#
DY
DY
A26
B5
F15
T21
H_DPSLP#
19
TEST6
DPSLP#
VCC
VCCP
D24
SB
F17
T6
DPWR#
H_DPWR#
7
VCC
VCCP
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
B22
D6
F18
V21
3
CPU_BSEL0
BSEL0
PWRGOOD
H_PWRGOOD
19
VCC
VCCP
1D5V_S0
layout note:
place C3 near
PIN B26
B23
D7
F20
W21
3
CPU_BSEL1
BSEL1
SLP#
H_CPUSLP#
7
VCC
VCCP
C21
AE6
AA7
3
CPU_BSEL2
BSEL2
PSI#
PSI#
35
VCC
AA9
B26
C156
VCC
VCCA
AA10
C26
VCC
VCCA
AA12
VCC
CPU_VID[0..6]
35
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
C161
SC10U10V5ZY-1GP
AA13
AD6
VCC
VID0
AA15
AF5
VCC
VID1
PLACE C173 close to the TEST4 PIN,
make sure TEST3,TEST4,TEST5 trace
routing is reference to GND and
away other noisy signals
AA17
AE5
VCC
VID2
AA18
AF4
VCC
VID3
AA20
AE3
VCC
VID4
AB9
AF3
VCC
VID5
AC10
AE2
VCC
VID6
AB10
VCC
B
Length match within
25 mils . The trace
width/space/other is
20/7/25 .
B
AB12
VCC
Resistor Placed
within 0.5" of CPU
pin. Trace should
be at least 25 mils
away from any other
toggling signal .
COMP[0,2] trace
width is 18 mils.
COMP[1,3] trace
width is 4 mils .
AB14
AF7
VCC_SENSE
VCC
VCCSENSE
VCC_SENSE
35
AB15
VCC
AB17
VCC
VSS_SENSE
AB18
AE7
VCC
VSSSENSE
VSS_SENSE
35
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
BGA479-SKT6-GPU3
BGA479-SKT6-GPU3
VCC_SENSE
1
2
VCC_CORE_S0
166
0
1
1
R99
R99
100R2F-L1-GP-U
100R2F-L1-GP-U
VSS_SENSE
1 2
R98 100R2F-L1-GP-U
R98 100R2F-L1-GP-U
200
0
1
0
Close to CPU pin
within 500mils
1D05V_S0
Close to CPU
pin AD26
Z0=55 ohm
with in
500mils .
R352
1KR2F-3-GP
<Core Design>
<Core Design>
<Core Design>
A
A
V_CPU_GTLREF
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R353
2KR2F-3-GP
Title
Title
Title
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
A3
A3
A3
Pamirs
Pamirs
Pamirs
-3
-3
-3
Date:
Date:
Date:
Friday, May 18, 2007
Friday, May 18, 2007
Friday, May 18, 2007
Sheet
Sheet
Sheet
of
of
of
41
41
41
5
5
5
5
4
3
2
1
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