HY29LV160BT-90

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HY29LV160
16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory
Single Power Supply Operation
– Read, program and erase operations from
2.7 to 3.6 volts
– Ideal for battery-powered applications
Data# Polling and Toggle Bits
– Provide software confirmation of
completion of program and erase
operations
High Performance
– 70, 80, 90 and 120 ns access time
versions
Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
Ultra-low Power Consumption (Typical
Values At 5 Mhz)
– Automatic sleep mode current: 1 µA
– Standby mode current: 1 µA
– Read current: 9 mA
– Program/erase current: 20 mA
Hardware Reset Pin (RESET#) Resets the
Device to Reading Array Data
Compliant With Common Flash Memory
Interface (CFI) Specification
– Flash device parameters stored directly
on the device
– Allows software driver to identify and use
a variety of different current and future
Flash products
Flexible Sector Architecture:
– One 16 KB, two 8 KB, one 32 KB and
thirty-one 64 KB sectors in byte mode
– One 8 KW, two 4 KW, one 16 KW and
thirty-one 32 KW sectors in word mode
– Top or bottom boot block configurations
available
Compatible With JEDEC standards
– Pinout and software compatible with
single-power supply Flash devices
– Superior inadvertent write protection
Sector Protection
– Allows locking of a sector or sectors to
prevent program or erase operations
within that sector
– Sectors lockable in-system or via
programming equipment
– Temporary Sector Unprotect allows
changes in locked sectors (requires high
voltage on RESET# pin)
Space Efficient Packaging
– 48-pin TSOP and 48-ball FBGA packages
Fast Program and Erase Times
– Sector erase time: 0.25 sec typical for
each sector
– Chip erase time: 8 sec typical
– Byte program time: 9
LOGIC DIAGRAM
20
8
µ
s typical
A[19:0]
DQ[7:0]
Unlock Bypass Program Command
– Reduces programming time when issuing
multiple program command sequences
7
CE#
DQ[14:8]
Automatic Erase Algorithm Preprograms
and Erases Any Combination of Sectors
or the Entire Chip
OE#
DQ15/A-1
WE#
RY/BY#
Erase Suspend/Erase Resume
– Suspends an erase operation to allow
reading data from, or programming data
to, a sector that is not being erased
– Erase Resume can then be invoked to
complete suspended erasure
RESET#
BYTE#
Automatic Program Algorithm Writes and
Verifies Data at Specified Addresses
Preliminary
Revision 1.2, May 2001
KEY FEATURES
100,000 Write Cycles per Sector Minimum
HY29LV160
GENERAL DESCRIPTION
The HY29LV160 is a 16 Mbit, 3 volt-only, CMOS
Flash memory organized as 2,097,152 (2M) bytes
or 1,048,576 (1M) words that is available in 48-
pin TSOP and 48-ball FBGA packages. Word-
wide data (x16) appears on DQ[15:0] and byte-
wide (x8) data appears on DQ[7:0].
The HY29LV160 can be programmed and erased
in-system with a single 3 volt V
CC
supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a higher voltage V
PP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as low as 80 ns over
the full operating voltage range of 2.7 - 3.6 volts,
and 70 ns with a limited voltage range of 3.0 - 3.6
volts, are offered for timing compatibility with the
zero wait state requirements of high speed mi-
croprocessors. To eliminate bus contention, the
HY29LV160 has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash memory command set stan-
dard. Commands are written to the command reg-
ister using standard microprocessor write timings.
They are then routed to an internal state-machine
that controls the erase and programming circuits.
Device programming is performed a byte/word at
a time by executing the four-cycle Program Com-
mand write sequence. This initiates an internal al-
gorithm that automatically times the program pulse
widths and verifies proper cell margin. Faster pro-
gramming times can be achieved by placing the
HY29LV160 in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29LV160’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command sequence. This
initiates an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
As during programming cycles, the device auto-
matically times the erase pulse widths and veri-
fies proper cell margin. Hardware Sector Protec-
tion optionally disables both program and erase
operations in any combination of the sectors of
the memory array, while Temporary Sector Un-
protect allows in-system erasure and code
changes in previously protected sectors. Erase
Suspend enables the user to put erase on hold for
any period of time to read data from, or program
data to, any sector that is not selected for era-
sure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) or DQ[6] (Toggle) status bits. Hard-
ware data protection measures include a low V
CC
detector that automatically inhibits write operations
during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com-
mand. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Two power-saving features are embodied in the
HY29LV160. When addresses have been stable
for a specified amount of time, the device enters
Automatic Sleep mode. The host can also place
the device into Standby mode. Power consump-
tion is greatly reduced in both of these modes.
Common Flash Memory Interface (CFI)
To make Flash memories interchangeable and to
encourage adoption of new Flash technologies,
major Flash memory suppliers developed a flex-
ible method of identifying Flash memory sizes and
configurations in which all necessary Flash device
parameters are stored directly on the device.
Parameters stored include memory size, byte/word
configuration, sector configuration, necessary volt-
ages and timing information. This allows one set
of software drivers to identify and use a variety of
different current and future Flash products. The
standard which details the software interface nec-
essary to access the device to identify it and to
determine its characteristics is the Common Flash
Memory Interface (CFI) Specification. The
HY29LV160 is fully compliant with this specification.
2
Rev. 1.2/May 01
 HY29LV160
BLOCK DIAGRAM
DQ[15:0]
A[19:0], A-1
STATE
CONTROL
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O BUFFERS
DQ[15:0]
WE#
CE#
OE#
BYTE#
COMMAND
REGISTER
I/O CONTROL
DATA LATCH
PROGRAM
VOLTAGE
GENERATOR
RESET#
RY/BY#
Y-DECODER
Y-GATING
V
CC
DETECTOR
TIMER
A[19:0], A-1
16 Mb FLASH
MEMORY
ARRAY
X-DECODER
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Rev. 1.2/May 01
3
HY29LV160
PIN CONFIGURATIONS
48-Ball FBGA (Top View, Balls Facing Down)
A6
B6
C6
D6
E6
F6
G6
H6
A[13]
A[12]
A[14]
A[15]
A[16]
BYTE# DQ[15]/A[-1]
V
SS
A5
B5
C5
D5
E5
F5
G5
H5
A[9]
A[8]
A[10]
A[11]
DQ[7]
DQ[14]
DQ[13]
DQ[6]
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
A[19]
DQ[5]
DQ[12]
V
CC
DQ[4]
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A[18]
NC
DQ[2]
DQ[10]
DQ[11]
DQ[3]
A2
B2
C2
D2
E2
F2
G2
H2
A[7]
A[17]
A[6]
A[5]
DQ[0]
DQ[8]
DQ[9]
DQ[1]
A1
B1
C1
D1
E1
F1
G1
H1
A[3]
A[4]
A[2]
A[1]
A[0]
CE#
OE#
V
SS
A[15]
A[14]
1
2
48
47
A[16]
BYTE#
A[13]
A[12]
3
4
46
45
V
SS
DQ[15]/A[-1]
A[11]
A[10]
5
6
44
43
DQ[7]
DQ[14]
A[9]
A[8]
7
8
42
41
DQ[6]
DQ[13]
A[19]
NC
9
10
40
39
DQ[5]
DQ[12]
WE#
RESET#
11
12
TSOP48
38
37
DQ[4]
V
CC
NC
NC
13
14
36
35
DQ[11]
DQ[3]
RY/BY#
A[18]
15
16
34
33
DQ[10]
DQ[2]
A[17]
A[7]
17
18
32
31
DQ[9]
DQ[1]
A[6]
A[5]
19
20
30
29
DQ[8]
DQ[0]
A[4]
A[3]
21
22
28
27
OE#
V
SS
A[2]
A[1]
23
24
26
25
CE#
A[0]
4
Rev. 1.2/May 01
 HY29LV160
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (V
IH
) causes assertion of the
signal. A ‘#’ symbol following the signal name, e.g.,
RESET#, indicates that the signal is asserted in
the Low state (V
IL
). See DC specifications for V
IH
and V
IL
values.
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
MEMORY ARRAY ORGANIZATION
The 16 Mbit Flash memory array is organized into
35 blocks called
sectors
(S0, S1, . . . , S34). A
sector is the smallest unit that can be erased and
that can be protected to prevent accidental or un-
authorized erasure. See the ‘Bus Operations’ and
‘Command Definitions’ sections of this document
for additional information on these functions.
In the HY29LV160, four of the sectors, which com-
prise the
boot block
, vary in size from 8 to 32
Kbytes (4 to 16 Kwords), while the remaining 31
sectors are uniformly sized at 64 Kbytes (32
Kwords). The boot block can be located at the
bottom of the address range (HY29LV160B) or at
the top of the address range (HY29LV160T).
Tables 1 and 2 define the sector addresses and
corresponding address ranges for the top and bot-
tom boot block versions of the HY29LV160.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 3 lists the normal bus operations,
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 4.
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host reads from an address
within an erase-suspended (or erasing) sector, or
while the device is performing a byte or word pro-
gram operation, the device outputs status data
instead of array data. After completing an Auto-
matic Program or Automatic Erase algorithm within
a sector, that sector automatically returns to the
read array data mode. After completing a program-
ming operation in the Erase Suspend mode, the
system may once again read array data with the
same exception noted above.
The host must issue a hardware reset or the soft-
ware reset command to return a sector to the read
array data mode if DQ[5] goes high during a pro-
gram or erase cycle, or to return the device to the
read array data mode while it is in the Electronic
ID mode.
Read Operation
Data is read from the HY29LV160 by using stan-
dard microprocessor read cycles while placing the
byte or word address on the device’s address in-
puts. The host system must drive the CE# and
OE# pins LOW and drive WE# high for a valid
read operation to take place. The BYTE# pin de-
termines whether the device outputs array data in
words (DQ[15:0]) or in bytes (DQ[7:0]).
The HY29LV160 is automatically set for reading
array data after device power-up and after a hard-
Rev. 1.2/May 01
5
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